基于现场可编程门阵列的数控延时器的设计  

Design of digitally programmable delay generator based on FPGA

作　　者：孙建东[1] 

机构地区：[1]南京理工大学电子工程与光电技术学院 江苏南京210094

出　　处：《国外电子元器件》2006年第9期27-30,共4页International Electronic Elements

摘　　要：给出一种基于现场可编程门阵列(FPGA)的数控延时器的设计方法。首先详细介绍使用计数器的串联实现可控延时的方法,接着讨论不同延时范围下该数控延时器的改进方案,最后分析延时误差及延时精确度。延时器的外部接口仿照AD9501设计。The design of digitally programmable delayer based on FPGA is given out in this paper, First,the method using counters in series to design programmable delayer, is introduced particularly. Then the resolvent at different time-lapse scope is discussed in detail. Lastly,the time-lapse error and precision of this digitally programmable delayer is analysed.The design of the external interface of the programmable delayer is like that of AD9501.

关 键 词：FPGA VHDL AD9501 数控延时器 雷达目标模拟器 

分 类 号：TN791[电子电信—电路与系统]