超深亚微米CMOS工艺参数波动的测量电路  

Research on a Measurement Circuit for UDSM CMOS Process Parameter Variation

作　　者：杨媛[1] 高勇[1] 余宁梅[1] 

机构地区：[1]西安理工大学电子工程系,西安710048

出　　处：《Journal of Semiconductors》2006年第9期1686-1689,共4页半导体学报（英文版）

基　　金：西安应用材料创新基金资助项目(批准号:XA-AM-200514)~~

摘　　要：分析了超深亚微米工艺参数波动对电路的影响;采用“放大”的思路设计了简单的用于测量超深亚微米工艺门延迟、动态功耗、静态功耗及其波动的电路,并提出了一种用于测量门延迟波动特性曲线的新型电路,该电路采用较短的反相器链可以得到超深亚微米工艺下门延迟波动特性曲线.电路在90nmCMOS工艺下进行了流片制作,得到了90nmCMOS工艺下的单位门延迟波动特性曲线.测得延迟的波动范围为78.6%,动态功耗的波动范围为94.0%,漏电流功耗的波动范围为19.5倍,其中以漏电流功耗的波动性最为严重.The main device parameter variations for UDSM processes are discussed briefly. Based on the ＂amplifying＂ idea, simple circuits for measuring the gate delay,dynamic power,leakage power, and their variations for a 90nm process are designed. A novel circuit that can get the gate delay variation curve for a UDSM process using shorter inverter link is presented. The circuits are fabricated using 9Ohm CMOS technology,and the variation curve for the 90nm CMOS process is obtained. The results show that the variation range is 178.6%, 194.0% for dynamic power,and 19.5 times for leakage power. Thus the leakage power variation is the most serious.

关 键 词：超深亚微米 门延迟 动态功耗 漏电流功耗 

分 类 号：TN432[电子电信—微电子学与固体电子学]