基于神经网络的数字电路多故障测试生成算法  

A multiple faults test generation algorithm based on neural networks for digital circuits

作　　者：赵莹[1] 吴丽华[2] 王轸[2] 

机构地区：[1]北华大学电气信息工程学院,吉林吉林市132021 [2]哈尔滨理工大学测控与通信工程学院,黑龙江哈尔滨150040

出　　处：《电机与控制学报》2006年第5期478-481,共4页Electric Machines and Control

摘　　要：针对数字电路中多故障测试生成效率较低的问题,提出了基于神经网络的数字电路多故障测试生成算法。依据故障转换方法把数字电路多故障测试生成问题转换成为单故障测试生成问题,采用神经网络的方法对单故障电路构造故障的约束网络,通过使用遗传算法求解故障约束网络能量函数的最小值点获得故障的测试矢量。在ISCAS’85国际标准电路上的实验结果表明,故障平均测试生成时间在0.017s以下,故障覆盖率在96%以上。与其他算法相比,测试生成效率明显提高。A multiple faults test generation algorithm based neural networks for digital circuits is proposed considering that the test generation efficiency for multiple faults in digital circuits is low. The test generation question for multiple faults of digital circuit is transformed into the test generation question for single fault based on method of faults transformation. The constraint network of the fault for the single fault circuit is constructed by using neural networks. The test vectors for faults can be obtained by solving the minimum of energy function of the constraint network for the fault with genetic algorithm. The experimental results on some ISCAS＇85 international standard circuits demonstrate the average test generation time for fault is shorter than 0. 017s and the faults coverage is higher than 96%. The test generation efficiency is higher comparing with other algorithms.

关 键 词：神经网络 遗传算法 约束网络 能量函数 

分 类 号：TN407[电子电信—微电子学与固体电子学]