采用动态译码缓存的高速指令集模拟器  

High Performance Instruction Set Simulator Using Dynamic Decode Cache

作　　者：桑胜田[1] 王进祥[1] 赵新曙 

机构地区：[1]哈尔滨工业大学微电子中心 [2]61081部队

出　　处：《计算机工程》2006年第18期248-250,共3页Computer Engineering

摘　　要：指令集模拟器是计算机体系结构研究和SoC软硬件协同设计的重要工具,模拟器的性能和灵活性是影响设计和验证效率的重要因素。解释型指令集模拟器具有很好的灵活性,在操作系统等涉及到自修改代码的模拟中具有不可替代的作用。该文给出了一个高性能解释型指令集模拟器的设计,它具有很高的模拟精度和很好的灵活性;同时指令集模拟器采用了动态译码缓存等优化技术,使其具有很高的模拟性能。以ARM7指令集模拟器为实例,所提出的优化技术同样适用于其它现代RISC体系结构。The ISS （instruction set simulator） is a key factor for the overall design efficiency. involving self-modifying code, for example OS. optimization techniques are used to improve the and the optimization techniques presented in this is an important tool for the SoC HW/SW co-design and co-verification. The simulator performance Interpretive simulators have great flexibilities and are indispensable in the simulation of software This paper presents a high performance interpretive ISS, dynamic decode cache and several other simulation speed significantly. An ARM7 instruction set simulator is implemented for illustration, paper are also applicable for most other modern RISC architectures.

关 键 词：指令集模拟器 动态译码缓存 软硬件协同设计 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]