VISA:基于动态二进制翻译优化技术的可扩展体系结构  

VISA:A Scalable Architecture Based on Dynamic Binary Translation

作　　者：唐遇星[1] 邓鹍[1] 窦勇[1] 周兴铭[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2006年第8期95-98,共4页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(90307001)

摘　　要：体系结构设计经常要在代码兼容和结构创新之间进行折衷。保证代码兼容的体系结构难以引入创新性的体系结构技术,或者导致最终结构变得相当复杂。本文提出一种基于动态二进制翻译优化的可扩展处理器结构VISA。VI-SA在实现兼容的前提下拓展了体系结构设计的空间。模拟结果显示,VISA性能优于现有的动态二进制翻译优化框架,并有更高的性能潜力和扩展空间。Architects always trade off between code compatibility and architecture novelty. To keep the backward compatibility of new architectures, new innovation will be too difficult to apply, or even tune the result architecture with terrible complexity. This paper presents VISA, a scalable processor architecture based on dynamic binary translation （BT） and optimization. Keeping the full compatibility, VISA extends the design space of architecture at the same time. Simulation shows that VISA is better than traditional BT. And it has further potential both in performance and scalability space.

关 键 词：二进制翻译 动态优化 微处理器 指令集体系结构 可扩展性 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]