LRU-Assist:一种高效的Cache漏流功耗控制算法  

LRU-Assist:An Efficient Algorithm for Cache Leakage Power Controlling

作　　者：张承义[1] 张民选[1] 邢座程[1] 王永文[1] 

机构地区：[1]国防科技大学计算机学院610室,湖南长沙410073

出　　处：《电子学报》2006年第9期1626-1630,共5页Acta Electronica Sinica

基　　金：国家自然科学基金(No.60376018;60273069;90207011)

摘　　要：随着集成电路制造工艺进入超深亚微米阶段,漏电流功耗在微处理器总功耗中所占的比例越来越大,在开发新的低漏流工艺和电路技术之外,如何在体系结构级控制和优化漏流功耗成为业界研究的热点.Cache在微处理器中面积最大,是进行漏流控制的首要部件.LRU是组相联Cache最常用的替换算法,而研究发现,访存操作命中LRU后半区的概率很低.LRU-Assist算法以Drowsy Cache、Cache Decay等控制策略为基础,在保证处理器性能不受影响的前提下,利用既有的LRU信息把Cache的关闭率平均提高了15%,大大降低了漏电流功耗.The leakage power issue is challenging high-performance microprocessor design,especially as feature size shrinks. Not only are low leakage technologies and circuits well researched, but also architectural control methods are studied hotly. Caches represent a sizable fraction of the total power consumption, so they need to be managed firstly. LRU is the most popular replacement algorithm used in set associative caches, but researches show that the latter blocks in LRU list are rarely accessed again. LRU-assist algorithm proposed in this paper exploits existing LRU information to expand the low leak portion in cache in addition to the time-based drowsy and decay mechanism. Simulation results show that the cache off ratio can be increased by 15% and leakage power is greatly saved with negligible performance overhead.

关 键 词：微处理器 cache功耗 漏电流 LRU-assist 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]