Turbo码编码器IP核设计及验证  

Design and Verification of Turbo Encoding IP Core

作　　者：武凯[1] 李明[2] 刘玲[2] 陆桂富[1] 

机构地区：[1]上海大学机电工程与自动化学院,上海200072 [2]上海大学微电子研究与开发中心,上海200072

出　　处：《上海大学学报（自然科学版）》2006年第5期462-466,共5页Journal of Shanghai University:Natural Science Edition

基　　金：上海市教委青年基金资助项目(03AQ85)

摘　　要：深入研究了Turbo码编译码理论,结合IMT-2000中W-CDMA标准进行编码器IP核设计,实现了两个分量编码器同时归零;对数据采用流水处理,并在内部加入了并串转换,使其方便地应用于编码器验证平台的SOPC系统中;采用QuartusⅡ开发工具在APEX20KE系列FPGA芯片上实现了具有高速性、可变码率的编码器,器件综合后最高频率达120 MHz,可以用于第三代移动通信系统.Encoding and decoding of turbo codes with the W-CDMA standard in IMT-2000 is introduced. The IP core of the encoder is designed with two component code encoders returning to zero simultaneously. In the encoders, data are processed with pipelining, and converted from parallel to serial form in order to be used in the verification platform of encoder in a SOPC system. The high-speed encoder with variable coding rate is realized on a hardware platform APEX20KE with Quartus Ⅱ software. The encoder can be used in 3G mobile communication systems as the maximum frequency reaches 120 MHz after synthesis.

关 键 词：TURBO码 编码器 QuartusⅡ IP核 

分 类 号：TN919.3[电子电信—通信与信息系统]