系统级芯片测试调度最优总线指定方法  

Optimal bus assignment scheme for system on chip test scheduling

作　　者：詹瑾瑜[1] 熊光泽[1] 

机构地区：[1]电子科技大学计算机学院,四川成都610054

出　　处：《计算机集成制造系统》2006年第10期1693-1697,共5页Computer Integrated Manufacturing Systems

基　　金：国家863/CIMS主题资助项目(2003AAIZ2210)~~

摘　　要：为了缩短采用系统级芯片设计的电子产品的测试时间,提出了一种基于遗传算法的系统级芯片测试调度总线指定方法。在该方法中,建立了最优测试调度的遗传算法模型。为了使算法过程更稳健,更快地趋近于全局最优解,在传统遗传算法的基础上引入了差分进化、精英策略、自适应变异等几种机制,并通过实验与基于整数线性规划的测试调度方法进行比较,结果表明,所需的测试时钟周期数较少,适应于测试大规模系统级芯片。To reduce testing time of electronic applications using System on Chip （SoC） design, an optimal bus assignment scheme based on genetic algorithm was presented for SoC test scheduling. A genetic algorithm model for optimal test scheduling was constructed. To make the solution process more stable and the results nearer to global optimal solution, differential evolution, elitism approach and self--adaptive mutation were introduced to the traditional genetic algorithm. The approach provided more optimal test time clock cycles, comparable to the Integer Linear Prograroming（ILP） formulation of similar problems, the comparison results indicated that this approach was more appropriate to test the large--scale SoC.

关 键 词：系统级芯片 测试调度 知识产权核 测试访问机制 遗传算法 差分进化 

分 类 号：TN407[电子电信—微电子学与固体电子学]