基于FPGA的PDH通信二次群分接器设计  

Design of Quadric Group Demultiplexer for PDH Communication Based on FPGA

作　　者：刘震[1] 景新幸[1] 高原[1] 

机构地区：[1]桂林电子科技大学通信与信息工程系,广西桂林541004

出　　处：《电声技术》2006年第11期33-36,共4页Audio Engineering

摘　　要：采用FPGA芯片10K30构建了一个PDH通信二次群分接器,可成功地从速率为8448Kbit/s的PDH通信二次群中捕获帧同步码并进行数据分流,还原为4路基群数据码流。给出了相应的硬件设计图以及部分VHDL源程序及仿真波形图。A design of quadric group demultiplexer for PDH（plesiochronous digital hierarchy） communication is discussed based on 10k30 FPGA（Field Programmable Gate Array）. The frame synchronization of the quadric group signal at the speed of 8 448 Kbit/s is detected and the quadric group signal is divided into four signals in FPGA by the VHDL（Very High Speed Intergrated Circuit Hardware Description Language） program. In addition, the plan of hardware and some of the VHDL codes and waveforms of simulation are also listed.

关 键 词：现场可编程门阵列 超高速集成电路硬件描述语言 准同步数字系列 分接器 

分 类 号：TN912[电子电信—通信与信息系统]