降维卡诺图在数字逻辑设计中的应用  

Application of Reduced-dimension Karnaugh Map in Numeral Logical Design

作　　者：倪树范[1] 

机构地区：[1]绵阳师范学院物理与电子信息工程系,四川绵阳621000

出　　处：《绵阳师范学院学报》2006年第5期118-121,共4页Journal of Mianyang Teachers＇ College

摘　　要：文章介绍了在数字逻辑电路设计中降维卡诺图的建立和应用。特别在用数据选择器实现组合逻辑函数中,利用降维卡诺图的方法较之教材中常见的用公式方法进行对照比较获得数据选择器输入信号与逻辑函数变量的关系,具有灵活、方便、不容易出错的优点。This paper discusses the foundation and the application of reduced - dimension Kamaugh map in numeral logical circuit design. Compared with the common formulary way employed in the textbook to contrast the relation of the input signal of the data selector and the logical function variable, the application of reduced - dimension Kamaugh map has many advantages, especially in the course of achieving assembled logical function by data selector. It is of better flexibility, convenience and less mistakes.

关 键 词：降雏卡诺图 逻辑设计 应用 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构] TP331[自动化与计算机技术—计算机科学与技术]