含存储器数字电路板的TPS开发研究  

Study on the Developing of TPS for Digital PCB with RAM Chips

作　　者：成本茂[1] 鞠艳秋[1] 王红[1] 杨士元[1] 

机构地区：[1]清华大学自动化系,北京100084

出　　处：《半导体技术》2006年第12期926-929,934,共5页Semiconductor Technology

基　　金：国家973计划资助项目(2005CB321604)

摘　　要：提出了含存储器数字电路板的两种测试矢量集(TPS)开发方案。对含少量存储器芯片的电路板采用结构化的测试方案,即将RAM等效成时序电路模型,利用时序电路ATPG软件进行测试生成。对以RAM为主的存储器板提出了一种功能测试方案,采取压缩地址空间的方法,对RAM阵列进行读写操作。实际应用证明,这两种方案较好地满足了实际应用中的需要。Two TPS developing methods for digital PCB with RAM chips were given. Structural test method was appropriate for test of digital PCB with few RAM chips, which used the sequential ATPG to generate the test pattern after RAM was converted to a sequential model. While for the memory board with a large amount of RAM chips, functional method was the first choice, which used a compressed address space and mainly considered the faults in the RAM array.

关 键 词：存储器 测试矢量集 结构测试 功能测试 

分 类 号：TN407[电子电信—微电子学与固体电子学]