一种高效的H·264 CABAC解码器的VLSI结构  

An efficient VLSI architecture of the CABAC decoder in H.264

作　　者：石迎波[1] 李云松[1] 张建龙[1] 

机构地区：[1]西安电子科技大学综合业务网理论与关键技术国家重点实验室,陕西西安710071

出　　处：《西安电子科技大学学报》2006年第6期844-848,891,共6页Journal of Xidian University

基　　金：国家自然科学基金重点项目(60532060);国家自然科学基金资助(60372043)

摘　　要：提出一种H.264/AVC中基于上下文的自适应二进制算术编码(CABAC)解码器的硬件设计方法,在采用并行结构的基础上,给出了一种高效的VLSI实现方案.采用两级有限状态机结构控制宏块解码过程,并通过对残差系数存储器的定时清零解决了数据存储耗时的问题,大大降低了解码控制的复杂度,从而提高解码速度,达到每1至2个时钟解出1比特.仿真结果表明,该方案能满足H.264/AVCmain profile CIF 30fps实时解码的要求.A hardware implementation of the Context-based Adaptive Binary Arithmetic Coding （CABAC） decoder for H. 264/AVC is presented. Based on the full use of the parallel architecture, an efficient solution for VLSI implementation is described. By developing the two-level finite state machines to control the decoding process and adopting the memory clear schedule to solve the problem of coefficients storage being time-consuming, the complexity of CABAC-decoder implementation is reduced, and the speed is increased to generate one bit within one or two cycles. Simulation results testify that our design can meet ,the needs of decoding the H. 264/AVC main profile CIF bit stream at 30fps in real time.

关 键 词：H.264/AVC CABAC解码器 大规模集成电路 有限状态机 

分 类 号：TN919.81[电子电信—通信与信息系统]