一种减少BIST测试资源的高级寄存器分配算法  

A high level register allocation algorithm for minimizing BIST test resources

作　　者：李杰[1] 李锐[1] 卜爱国[1] 王超[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,江苏南京210096

出　　处：《电路与系统学报》2006年第6期91-95,共5页Journal of Circuits and Systems

基　　金：国家自然科学基金资助课题(60176018)

摘　　要：在高级综合阶段考虑电路的可测性有许多优点,包括降低硬件开销,减少性能的下降,并达到更高的测试效率等。本文提出了一种基于伪随机可测性方法的寄存器分配算法,来减少内建自测试(BIST)所带来的硬件开销。在基准电路上的实验结果表明:与其它BIST测试综合方法相比较,采用本论文所提的方法进行测试综合对测试资源占用最多可以降低46.8%。Considering testability during high level synthesis has several benefits, including reducing area overhead and performance degradation, improving test effectiveness and so on, In this paper, we present a register allocation algorithm based on pseudo-random testability metrics for minimizing Built-in Selftest （BIST） resources. Through a variety of synthesis benchmarks, experimental results show that the test resources reduction of up to 46.8% can be achieved by comparison with other BIST synthesis methods.

关 键 词：内建自测试 寄存器分配算法 自可测性 测试 

分 类 号：TN74[电子电信—电路与系统]