基于EPP并口的视频芯片验证  

EPP Based Verification Scheme for Video Chip

作　　者：梅魁志[1] 黄畅[1] 曾强[1] 吴奇[1] 

机构地区：[1]西安交通大学人工智能与机器人研究所,陕西西安710049

出　　处：《微电子学》2006年第6期718-721,728,共5页Microelectronics

基　　金：国家自然科学基金创新群体研究资助项目(60021302);国家高技术研究发展计划资助项目(2005AA1Z1272)

摘　　要：增强型并口(EPP)是一种PC机与外设之间简单而可靠的通讯手段。文章使用硬件描述语言Verilog,实现了基于该协议数据读写规范的EPP上传和下载IP核设计,以标准的同步FIFO接口,为FPGA原型与PC机提供实时芯片验证的中间输出和测试矢量输入。并以JPEG2000编码芯片和数字视频解码芯片的验证实例,说明了该IP核在复杂芯片设计的实时验证中的有效应用。Enhanced Parallel Port （EPP） is a simple and reliable means for communication between PC and pe ripherals. Its reading and writing data protocol is used to implement the EPP_Upload and EPP Download IP with standard synchronous FIFO-like interface in hardware description language of Verilog. The EPP IPs provide ways for outputing intermediate results and inputing test vectors between FPGA prototype and PC in real time verification process in ASIC design. The verification of a JPEG2000 encoder chip and digital video decoder chip validates the effectiveness of EPP IP.

关 键 词：EPP IP核 验证 JPEG2000编码器 数字视频解码器 

分 类 号：TN402[电子电信—微电子学与固体电子学]