两倍增益10位100 MSPS CMOS采样/保持电路  

A 10-Bit 100 MSPS CMOS Sample-and-Hold Circuit with Double Gains

作　　者：王浩娟[1] 吴霜毅[1] 宁宁[1] 于奇[1] 王向展[1] 范龙[1] 

机构地区：[1]电子科技大学微电子与固体电子学院,四川成都610054

出　　处：《微电子学》2006年第6期802-805,共4页Microelectronics

摘　　要：提出了一种两倍增益高线性、高速、高精度采样/保持电路。该采样/保持电路通过对输入信号实现两倍放大,改善了高频非线性失真;一种新型的消除衬底偏置效应的采样开关,有效地提高了采样的线性度;高增益和宽带宽的折叠共源共栅运算放大器保证了采样/保持电路的精度和速度。整个电路以0.35μm AMS Si CMOS模型库验证。模拟结果显示,在输入信号为49.21875MHz正弦波,采样频率为100 MHz时,增益误差为70.9μV,SFDR可达到84.5 dB。A high linearity, high speed and high resolution sample-and-hold circuit with double gains is proposed. The circuit improves high-frequency nonlinear distortion by double amplifying input signals, A novel sampling switch capable of eliminating substrate bias effect is used to increase the sampling linearity. A folded cascode operational amplifier with high DC gain and unity gain frequency is designed to maintain the resolution and settling time of the sample-and-hold circuit, Simulation, which is performed in Cadence environment with 0.35 μm AMS Si CMOS models, shows that the circuit has a gain error of 70. 9 μV and an SFDR up to 84.5 dB at 100 MHz sampling rate with 49. 21875 MHz input sinewaves.

关 键 词：采样/保持电路 非线性 衬底偏置效应 

分 类 号：TN432[电子电信—微电子学与固体电子学]