高性能双模前置分频器设计  

Design of High Performance Dual Modulus Divider-by Prescaler

作　　者：曾健平[1] 谢海情[1] 晏敏[1] 曾云[1] 章兢[2] 

机构地区：[1]湖南大学应用物理系,长沙410082 [2]湖南大学电气与信息工程学院,长沙410082

出　　处：《半导体技术》2007年第1期65-67,73,共4页Semiconductor Technology

基　　金：湖南省自然科学基金资助项目(05JJ30115)

摘　　要：提出了一种新颖的分频器设计方案,在高频段采用改进的CMOS源耦合逻辑(SCL)结构的主从D触发器进行分频,以满足高速要求;在低频段采用自锁存的D触发器进行分频。这种结构的D触发器不但具有锁存功能,而且所需的管子比主从式D触发器要少,以满足低功耗和低噪声要求。从而使总体电路实现高速、低功耗、低噪声要求。基于TSMC的0.18μmCMOS工艺,利用Cadence Spectre工具进行仿真。该分频器最高工作频率可达到5 GHz,在27℃、电源电压为1.8 V、工作频率为5 GHz时,电路的功耗仅4.32 mW。A novel design plan of divider was presented. In the higher frequency band, M/S DFF structured by CMOS SCL was used to divide to satisfy the high speed command. In the lower frequency band, DFF with self-latch function was used. This structure has locked function, also has less MOS transistor than M/S DFF. So it satisfies the command of lower power and noise. The whole system could realize high-speed, low-power, low-jitter. The circuit was simulated by Cadence Spectre under the CMOS technology of TSMC 0. 18 μm. The highest frequency of the divider is up to 5 GHz. When T = 27℃, VDD = 1.8 V, f= 5 GHz, the power consumption was only 4.32 mW.

关 键 词：分频器 源耦合逻辑 D触发器 互补金属氧化物半导体 

分 类 号：TN772[电子电信—电路与系统]