FPGA有限状态机模拟I^2C总线设计  

Design of FSM simulation for I^2C bus based on FPGA

作　　者：潘小冬[1] 陈泽祥[1] 黄自力[2] 高升久[2] 

机构地区：[1]电子科技大学光电信息学院,四川成都610054 [2]西南技术物理研究所,四川成都610041

出　　处：《中国测试技术》2007年第1期105-107,共3页CHINA MEASUREMENT & TESTING TECHNOLOGY

摘　　要：以I2C总线协议为根据,用有限状态机(FSM:Finite State Machine)设计了基于FPGA的I2C初始化程序模块。主要内容包括简述I2C总线的特点;介绍用FPGA中FSM开发I2C总线模块时的设计思想和实现过程;给出并解释了部分用Verilog HDL描述I2C总线初始化SAA7111和SAA7121的程序,最后在QuartusII中进行了I2C总线主从模式下的时序仿真和用其内嵌逻辑软分析仪SignalTapII完成了硬件调试。According to I^2C bus communication protocol, this paper introduced design of the I^2C bus by FSM on FPGA. It mainly includes the brief introduction of the characteristic of F＇C bus, the design ideas and implementation process for I^2C bus based on FPGA. Then it share and explanation some program of initialization for SAA7111 and SAA7121 in Vcrilog HDL Finally timing simulation under master-slave in QuartusⅡ was done, and debugging by SignalTapII on hardware was completed successfully.

关 键 词：I^2C总线 FPGA 有限状态机(FSM) VERILOG HDL 初始化 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]