基于FPGA的数字图像中值滤波器设计  

Design of Median Filter for Digital Image Based on FPGA

作　　者：徐大鹏[1] 李从善[2] 

机构地区：[1]中国科学院长春光学精密机械与物理研究所 [2]西安卫星测控中心,陕西渭南714000

出　　处：《电子器件》2006年第4期1114-1117,共4页Chinese Journal of Electron Devices

摘　　要：在电视跟踪系统中,为了抑制数字视频图像存在的脉冲噪声和满足系统实时性的需要,对图像进行基于硬件的实时滤波处理是有重要意义的。通过分析常见的3×3滤波窗口的数学模型,提出了基于FPGA的中值滤波算法及其设计方案。结合现场可编程门阵列FPGA的并行结构和适合流水线设计的结构特点,采用VHDL语言进行电路设计,利用仿真工具MODELSIM进行时序仿真验证。实际应用中表明可以滤除脉冲噪声,有效地改善了图像的质量,满足系统的实时性要求,提高了系统性能。In the television tracking system, real-time filtering based on hardware is very significant to meet the demands of real-time image process and to restrain pulse noise. The mathematical model of 3 × 3 template is analyzed and a new median filter algorithm and corresponding solution based on FPGA is presented. FPGA can realize concurrent and pipeline architecture efficiently, and is used as hardware platform to realize the algorithm. The design is described with VHDL, Verified through MODELSIM simulator. Result shows the design can filter pulse noise and improved the quality of image, in application, met system real-time demands, improved the performances of system.

关 键 词：FPGA 中值滤波 实时处理 数字视频图像 流水线 

分 类 号：TN911.73[电子电信—通信与信息系统]