MPEG-4视频编码器MacroBlockIP模块的VLSI结构设计  

VLSI Architecture of Macro BlockIP Module in MPEG-4 Video Codec

作　　者：刘大明[1] 王占辉[1] 

机构地区：[1]海军工程大学电气与信息工程学院,武汉430033

出　　处：《电子器件》2006年第4期1158-1163,共6页Chinese Journal of Electron Devices

摘　　要：设计了MPEG-4视频编码器中用于处理纹理部分的模块-MacroBlockIP模块。它主要由重复填充、运动补偿、纹理填充、二维DCT/IDCT、量化/反量化和DC/AC预测六个部分组成。文中的方案在Xilinx ISE6.1i集成开发环境下用VHDL语言进行描述,并使用电子设计自动化(EDA)工具进行了模拟和验证。试验结果表明,所设计的MacroBlockIP模块逻辑功能正确,满足MPEG-4 Core Profiles&Level2的实时编码要求,可用于MPEG-4视频编码器的VLSI实现。This paper presents the VLSI architecture for the MacroBlocklP module of video encoding according to the MPEG-4 standard. The pixel compression module, which consists of the repetitive padding, the motion compensation, the texture padding, 2D-DCT/IDCT, Q/IQ, the AC/DC prediction, supports＇the tools for the texture processing part in MPEG-4 codee. The VLSI architecture and implementation in terms of VHDL are designed in the Xilinx ISE6. li environment and some simulations are carried out in tools of electronic design automation （EDA）. The experimental results show that the VLSI processor designed in this paper can perform correct logic functions and can achieve a real-time coding for MPEG-4 Core Profile and Level 2.

关 键 词：MPEG-4 超大规模集成电路 视频编码器 

分 类 号：TN47[电子电信—微电子学与固体电子学]