实现折叠共栅共源运放MST的时钟馈通频率补偿方法  

Implementation of Folded-Cascode OTA’s MST State via Clock Feedthrough Frequency Compensation

作　　者：王向展[1] 宁宁[1] 于奇[1] 戴广豪[1] 杨谟华[1] 

机构地区：[1]电子科技大学微电子与固体电子学院,成都610054

出　　处：《电子与信息学报》2007年第3期743-746,共4页Journal of Electronics & Information Technology

摘　　要：该文基于二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种新型的时钟馈通频率补偿方法。该方法通过MOS电容引入时钟馈通进行频率补偿,无需对运放结构和参数进行调整。在Cadence ADE仿真环境下运用SMIC 0.35μm 2P3M Polyside Si CMOS模型参数,对折叠共源共栅放大器进行了模拟分析。结果表明,补偿后的运放实现了MST状态,并缩短了建立时间22.7%,提高了其响应速度。在0.5pF^2.5pF负载电容范围内,其建立时间近似线性变化,且对应每一负载电容值均达到MST状态。该方法可望应用于高速有源开关电容网络及其相关领域。In this article, a novel Clock Feedthrough Frequency Compensation （CFFC） method based on the Minimum-Settling-Time （MST） theory and step-response analysis of a second order system is presented. Cadence ADE simulation results of a folded-cascode OTA with CFFC designed with SMIC 0.35μm 2P3M Polyside Si CMOS models show that the settling time of the CFFC compensated cascode OTA is reduced by 22.7%, MST state is obtained as well. With the capacitor load varies from 0.5pF to 2.5pF, the settling time changes linearly from 3.62ns to 4.46ns, and the circuit achieves MST state at each load value. This method can be applied to high-speed active switched capacitor networks and its related fields.

关 键 词：最小建立时间 时钟馈通 快速建立 折叠式共源共栅运放 开关电容网络 

分 类 号：TN722[电子电信—电路与系统]