新型低噪声电流型CMOS边沿触发器设计  

Novel Current-mode CMOS Edge-triggered Flip-flops with Low-noise

作　　者：杭国强[1] 任洪波[2] 

机构地区：[1]浙江大学信息与电子工程学系,杭州310027 [2]浙江大学计算中心,杭州310028

出　　处：《固体电子学研究与进展》2007年第1期95-99,共5页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(No.60273093);浙江省自然科学基金资助项目(No.Y106375)

摘　　要：提出以电流信号表示逻辑值的新型低噪声触发器设计,用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。所提出的设计包括主从型边沿触发器和单闩锁单边沿触发器。单个锁存器的电流型边沿触发器设计是通过在有效时钟沿后产生的窄脉冲使锁存器瞬时导通完成一次取样求值。与主从型触发器相比,单闩锁结构的触发器具有结构简单、直流功耗低的特点。采用0.25μm CM O S工艺参数的HSP ICE模拟结果表明,所提出的电流型触发器工作时,在电源端产生的电流波动远远小于传统的CM O S电路。Some new low-noise edge triggered flip-flops are presented, and their logic levels are realized in the current domain by steering a constant dc bias current. These flip-flops include master-slave configuration, and one-latch single edge-triggered（1L-SET） flip-flop. In one-latch single edged-triggered configuration, data are sampled into the latch during a short transparency period for one edge of the clock signal. In comparison with master-slave flip-flop, the one-latch configuration has reduced transistor count and lower static power consumption. HSPICE simula- tions using 0.25 μm CMOS technology have shown that the current spikes due to switching are much reduced in the proposed flip-flops with respect to conventional CMOS circuits. The reduction in digital switching noise allows the development of higher performance on-chip analog circuitry in CMOS mixed-mode applications.

关 键 词：电流型互补金属氧化物半导体电路 混合集成电路 触发器 低噪声设计 

分 类 号：TN432[电子电信—微电子学与固体电子学]