数字集成电路测试矢量的生成  

Produce of Generate Test Vector in the Testing of Digital Integrated Circuits

作　　者：刘伟[1] 

机构地区：[1]桂林电子科技大学计算机辅助测试教研室,广西桂林541004

出　　处：《电子与封装》2007年第4期18-20,48,共4页Electronics & Packaging

摘　　要：电路的日益复杂和集成度的不断提高,使测试已成为集成电路设计中费用最高、难度最大的一个环节。文章主要讨论了测试中伪随机测试矢量的生成,并提出了改进其周期的办法,从而大大提高了故障的覆盖率。最后通过硬件描述语言Verilog在Quartus Ⅱ软件下进行仿真,验证了其正确性。Nowadays, integrated circuits are becoming more and more complex and high- integrated. Testing has become a high-expenditure and most difficult tache in the design of integrated circuits. This paper mainly discusses how to generate random test vector and propose a new method to improve it＇s period. Based on the analysis, it improves the fault coverage .Simulation which uses hardware description language Verilog in the Quartus？ software environment corroborate the results.

关 键 词：随机测试序列 硬件描述语言Verilog 同余伪随机序列 线性反馈移位寄存器 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]