新型低功耗8位250 MSPS 3级Flash A/D转换器  

A Novel Low Power 8-Bit 250 MSPS Triple-Stage Flash A/D Converter

作　　者：宁宁[1] 于奇[1] 范龙[1] 吴霜毅[1] 刘国庆[1] 刘源[1] 杨谟华[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《微电子学》2007年第2期238-241,共4页Microelectronics

基　　金：国家自然科学基金资助项目(60072004)

摘　　要：为了降低A/D转换器(ADC)的功耗和面积,基于Flash ADC原理,利用分级比较方式,减少ADC比较器数目,并源自全新的基准区间选通逻辑模块,替代MDAC和残差放大单元;针对8位分辨精度,提出了一种新型3级Flash ADC架构,并依此结构,设计实现了一个8位250 MSPSADC。0.35μm/3.3 V AMS Si-CMOS工艺模型和版图验证结果表明,在实现250 MSPS前提下,DNL<±0.4 LSB,INL<±0.5 LSB;Nyquist频率下,SFDR为59.2 dB,功耗85 mW,面积1.20mm×8 mm。对比同类ADC,功耗与面积指标明显占优。该系统架构可望应用于高速低功耗混合信号处理电路的研究和开发。Based on the principle of flash A/D converter （ADC）, a novel triple-stage flash ADC; architecture is proposed for 8-bit resolution, to reduce power dissipation and area, which is realized by using segmented comparison to reduce the number of comparators and substituting a new reference region selecting cell for MDAC and residue amplifier. Taking advantage of this architecture, an 8-bit 250 MSPS AIX; is designed. Simulation with 0. 35 μm/3. 3 V AMS Si-CMOS process models and layout show that the ADC achieves a DNL〈 ±0. 4 LSB, INL〈±0. 5 LSB, and an SFDR of 59. 2 dB with 250 MSPS at Nyquist frequency. The device dissipates 85 mW of power and occupies a chip area of 1. 2 mm×0. 8 mm Compared with other similar 8-bit ADCs, its power dissipation is much lower.

关 键 词：3级Flash A/D转换器 比较器 高速低功耗 基准区间选通逻辑 

分 类 号：TN432[电子电信—微电子学与固体电子学]