一种高阶1 bit插入式∑-Δ调制器的设计  

Design of a High-Order 1-Bit Interpolative Sigma-Delta Modulator

作　　者：周浩[1] 曹先国[1] 李家会[1] 

机构地区：[1]西南科技大学信息工程学院,四川绵阳621010

出　　处：《半导体技术》2007年第2期147-149,166,共4页Semiconductor Technology

基　　金：国家863课题项目(2003AA116060)

摘　　要：介绍了插入式∑-△A／DC调制器的设计过程,并给出了调制器行为级SIMULINK模型,通过对调制器系统级仿真可以确定调制器的信噪比、增益因子等参数,为其电路设计提供依据。设计了一个4阶调制器,仿真结果显示在128的过采样比、输入信号相对幅度-6 dB的条件下,可获得110 dB的信噪比,达到18 bit的分辨率。Method for designing an interpolative sigma - delta modulator was presented, and modulator behavioral modeling based on SIMULINK was introduced. System level simulation of modulator can acquire SNR, GAIN coefficient, which are useful to circuit design. 4-order modulator was designed, simulation results show that with the oversampling ratio selected 128 and relative magnitude of input - 6dB, the modulator achieves SNR of 110dB, the resolution power is 18bit.

关 键 词：∑-△调制器 过采样 仿真 

分 类 号：TN761[电子电信—电路与系统]