基于低功耗双边沿T触发器的异步时序电路设计  

Design of Asynchronous Sequential Circuit Based on Low Power Double-edge-triggered T Flip-flop

作　　者：赵敏笑[1] 陈桂兰[1] 陈偕雄[2] 

机构地区：[1]金华职业技术学院,浙江金华321017 [2]浙江大学信息与电子工程系,杭州310028

出　　处：《科技通报》2007年第3期430-433,共4页Bulletin of Science and Technology

摘　　要：从T触发器的逻辑功能入手,介绍了基于单边沿T触发器和双边沿T触发器的同步时序电路设计方法,并在分析异步触发条件的基础上,分别给出了基于单边沿T触发和双沿T触发器2n进制异步计数器的设计公式。在此基础上,讨论用双边沿T触发器设计异步时序电路的方法,以十二进制计数器的设计为例验证了设计的正确性。Starting from the logic function of the T flip-flop, this paper introduces the logic design method of synchronous sequential circuit consisting of single-edge-riggered T flip-flop and double-edge-triggered T flip-flop. This paper also analyzes asynchronous ripple condition and gives out the expressions of module-2^n counters consisting of T flip-flop. Besides, it discusses the logic design of asynchronous sequential circuit based on double-edge-triggered T flip-flop, gives out a practical design example to show the design method for asynchronous module-12 counter. The design example shows that the design method presented here is effective.

关 键 词：低功耗 双边沿触发器 计数器 异步时序电路 逻辑设计 

分 类 号：TN911.23[电子电信—通信与信息系统]