纳米集成电路静态功耗机理及低功耗设计技术  

Static Power Mechanism and Low-Power Design Techniques in Nanometer CMOS Circuits

作　　者：徐懿[1] 李丽[1] 高明伦[1] 黄壮雄[1] 杨盛光[1] 

机构地区：[1]南京大学物理系微电子设计研究所

出　　处：《微电子学与计算机》2007年第5期184-188,192,共6页Microelectronics & Computer

基　　金：国家自然科学基金(90307011);江苏省高技术研究项目(BG2005030)

摘　　要：对当前纳米级低功耗设计中静态功耗的产生机理以及各种降低漏电流功耗的电路设计理论及其特点做详细的论述,以期为相关研究、设计人员提供有益参考。Due to the popularity of portable electronic system, Power is becoming more and more important in nanometer CMOS circuits as well as area and speed for designing VLSI. The source of power consumption is changing evidently in nanometer CMOS circuits. The leakage current is going to be the main contributor to power dissipation. All leakage mechanisms contributing to the off-state current are explored and different circuit techniques to reduce the leakage power are discussed in this paper in order to provide some valuable reference for related research and design work.

关 键 词：低功耗设计 阈值电压 堆垛效应 

分 类 号：TN431[电子电信—微电子学与固体电子学]