基于模拟存储器的FPGA原型验证系统  

A FPGA-Prototype Verification System Based on Simulated Memory

作　　者：张明[1] 周宏伟[1] 张民选[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2007年第6期87-88,131,共3页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(60376018);国家863计划资助项目(2005AA110020)

摘　　要：当前ASIC功能验证流程中,FPGA原型验证系统的可调试性一直是制约验证速度的重要障碍。本文提出了一种模拟存储器技术,即将FPGA板上的存储请求映射到PC机上,由PC机上的软件模拟存储器的行为。通过此技术,功能验证工程师可以非常方便地记录和分析测试用例的执行轨迹,以及设置访存事务级的断点等,大大增加了验证板的可调性。同时,模拟存储系统的设计复杂度和成本也低于由硬件实现的大容量存储系统,有助于降低FPGA原型验证板的设计复杂度。In the current ASIC functional verification flow, the debuggability for FPGA-prototype verification systems is a main obstacle that restricts the verification speed. A new simulated memory technology is provided in this paper. In this technology, memory accesses in the FPGA board are mapped to a PC and simulated by software. Functional verification engineers can record and analyze the executing track of test use cases,and set the breakpoints of the memory access transactional level conveniently, which greatly improves the debuggability of the verification board. Meanwhile, the complexity and cost of simulated memory are lower than actual hardware with a large memory system, which is helpful to decrease the complexity of the FPGA-prototype verification board.

关 键 词：ASIC FPGA 模拟存储器 功能验证 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]