CMOS低噪声放大器中的输入匹配研究与设计  

Research and Design of Input Matching Architecture in CMOS LNA

作　　者：张炜[1] 冯全源[1] 

机构地区：[1]西南交通大学信息科学与技术学院,成都610031

出　　处：《半导体技术》2007年第6期486-489,共4页Semiconductor Technology

基　　金：国家自然科学基金资助项目(60371017)

摘　　要：分析了低噪声放大器设计中最常用的源极电感负反馈输入匹配结构，指出其存在的缺陷及如何改进，即利用一个小值LC网络代替大感值的栅极电感Lg，同时移除源极负反馈电感Ls。应用这种改进型输入匹配结构，基于0．18μm BSIM3模型设计了工作频带为5．1—5．8GHz的宽带CMOS低噪声放大器。结果表明，虽然输入匹配由于移除源极负反馈电感Ls受到一定影响，但是有利于降低噪声系数并减小实际制作的芯片面积。The most common input impedance matching architecture in LNA designs was analyzed, which was the source inductive degeneration architecture. The architecture had some limitation and needed to be modified. A LC network was used instead of the large value gate inductor Lg and the source degeneration inductor Ls was removed. Based on this modified input matching architecture and 0.18 μm BSIM3 model, a wideband CMOS LNA whose operation frequency band was around 5.1 - 5.8GHz was presented. Results show that although the input impedance matching is a litter degraded due to the removal of the traditional source inductor Ls, it＇ s in favor of lower noise figure and smaller chip area.

关 键 词：低噪声放大器 输入阻抗匹配 互补金属氧化物半导体 

分 类 号：TN454[电子电信—微电子学与固体电子学]