基于0.18μm CMOS工艺8bit/150MHz折叠插值ADC  

0.18μm CMOS 8bit/150MHz Folding and Interpolation ADC

作　　者：周蕾[1] 李冬梅[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《半导体技术》2007年第6期524-527,531,共5页Semiconductor Technology

基　　金：国家自然科学基金(60475018);国家高技术(863)重大专项基金(2003AA1Z1100)

摘　　要：折叠插值模数转换器的转换速度快,可实现并行一步转换,但由于受到面积、功耗以及CMOS工艺线性度和增益的限制,其精度较低。提出了一种电流模均衡电路,能够有效地消除折叠电路中的共模影响,提高折叠电路增益及线性度,从而提高电路的转换精度。应用此技术,设计了一款折叠插值A/D转换器,工作电压为3.3 V,采样时钟为150 MHz,并通过0.18μmCMOS工艺实现,版图总面积为0.22 mm2。Folding and interpolation A/D converter is widely used with high speed and one-step conversion. However, it may call for a large power consume, and the precision is limited according to the less linear and smaller gain of CMOS process. A current circuit for averaging was introduced to avert the affection of common plus, boost the gain of the folder and advance the linearity of the folding circuit. An 8bit, 150 MHz folding and interpolation ADC with this averaging circuit was designed. The ADC is implemented in 0. 18 μm CMOS mix-signal process and it takes 0.22 mm^2 silicon area.

关 键 词：折叠 插值 模数转换器 电流模 均衡 

分 类 号：TN4[电子电信—微电子学与固体电子学]