基于CPLD的测试系统接口设计  

Design Testing System Interface Based on CPLD

作　　者：高相铭[1] 李国伟[1] 

机构地区：[1]安彩集团,河南省安阳市455000

出　　处：《电子工程师》2007年第6期19-21,33,共4页Electronic Engineer

摘　　要：介绍了一种用CPLD(复杂可编程逻辑器件)作为核心控制电路的测试系统接口,通过对CPLD和TTL电路的比较及CPLD在系统中实现的强大功能,论述了CPLD在测试系统接口中应用的可行性和优越性,简单介绍了VHDL在CPLD设计中的应用。实验证明用CPLD实现的电路具有集成度高、灵活性强、可靠性高、易于升级和扩展等特点。给出了主要电路图和时序仿真图。This paper describes a kind of testing system interface using CPLD as the central control circuit, and discusses the feasibility and advantage of using CPLD in the testing system interface through comparing CPLD with TTL circuit and introducing the powerful function of CPLD in the system. It introduces the application of VHDL in CPLD design. The experiment has proved the circuits using CPLD have many excellence ,for example, high integration degree, powerful agility, high reliability and powerful expansibility. The paper gives primary circuit diagram and emulate diagram.

关 键 词：CPLD 测试系统接口 VHDL 

分 类 号：TM930.9[电气工程—电力电子与电力传动]