浮点LMS算法的FPGA实现  

FPGA Implementation of Floating-point LMS Algorithm

作　　者：杜勇[1] 刘帝英[1] 

机构地区：[1]酒泉卫星发射中心,甘肃省酒泉市732750

出　　处：《电子工程师》2007年第6期58-60,共3页Electronic Engineer

摘　　要：LMS(最小均方)算法因其优良的收敛特性及算法简单等特点在自适应滤波器等领域得到了广泛的应用。浮点运算因其运算步骤繁琐及硬件资源消耗大等缺点使得浮点LMS算法的硬件实现十分困难。文中根据多输入高效浮点加法器结构在FPGA(现场可编程门阵列)上实现了浮点LMS算法。测试结果表明,实现后的LMS算法硬件资源消耗较少且收敛性能与理论值接近。LMS （Least Mean Square） Algorithm has been widely used in the adaptive filter design and etc, for its high-speed convergence and simple computation. The hardware implementation is very difficult because of floating-point arithmetic disadvantage of complex computation and too much hardware resource consuming. Floating-point LMS Algorithm is implemented successfully based on the multi-input structure-efficient floating-point adder presented. Test results show that the LMS Algorithm, which is implemented on FPGA, consumes little hardware resources and has almost the same convergence properties as the theoretical value.

关 键 词：浮点运算 浮点加法器 LMS算法 FPGA 

分 类 号：TP332.2[自动化与计算机技术—计算机系统结构]