一款低功耗异步FIFO的设计与实现  

Design and Realization of a Low Power Asynchronous FIFO

作　　者：张英武[1] 杜波[1] 袁国顺[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《电子器件》2007年第3期962-964,共3页Chinese Journal of Electron Devices

摘　　要：我们在异步FIFO(First In First Out)设计中,引入了门控时钟技术降低了控制电路和译码电路80%的功耗;并采用位线分割技术降低了存储单元38%的功耗.利用格雷码作异步FIFO指针的控制电路,能有效消除多时钟域中的亚稳态.基于CSMC0.6μm标准单元库的半定制设计流程对其进行设计和实现:使用Verilog硬件描述语言,利用Modelsim进行时序和功能仿真、Synopsys DC完成逻辑综合、SE实现自动布局布线.The paper introduces clock-gating technology in asynchronous FIFO（First In First Out） design, it effectively reduces the control logic and decode circuit 80% power; the memory cells reduce 38% power through divided-bit-line technology. The asynchronous FIFO control logics adopt a novel circuit using Gray code as the point of the asynchronous FIFO, which can eliminates metastability efficiently. The circuit is designed with semi-custom flow which is based on CSMC 0.6 μm digital standard cell library. The design uses Verilog hardware language, adopts Modelsim to simulate, Synopsys DC to realize logic synthesis and SE to achieve automatic placing and routing. The FIFO is realized by CSMC 0. 6 μm process.

关 键 词：异步FIFO 低功耗设计 门控时钟 格雷码 位线分割 

分 类 号：TP316[自动化与计算机技术—计算机软件与理论]