基于FPGA的实时图像中值滤波设计  

Design of Real-Time Image Median Filtering Based on FPGA

作　　者：朱捷[1] 朱小娟[2] 贺明[1] 

机构地区：[1]防空兵指挥学院,河南郑州450052 [2]郑州铁路职业技术学院,河南郑州450052

出　　处：《计算机测量与控制》2007年第6期798-800,共3页Computer Measurement &Control

摘　　要：在嵌入式图像处理系统中,图像处理的实时性问题一直是一个很难突破的设计瓶颈,特别是数据处理量大,实时性要求较为苛刻的场合,传统的MCU根本无法适应;利用现场可编程门阵列(FPGA)并行处理的优势,开发了一种适于硬件并行处理的图像中值滤波算法,并用VHDL硬件开发语言在ALTERA的Stratix中现场可编程门阵列(FPGA)上实现,给出了整个硬件系统的构造方法;仿真结果说明该算法可以满足实时性要求,取得了良好的滤波效果,适用于图像采集与预处理系统中。Real-time image processing is a difficult problem in embedded image processing system. The traditional MCU is had to adapt the large volume data processing. FPGA （Programmable Logic Device） is an effective driver to realize real-time parallel processing of data. This article makes use this characteristic of FPGA for solution of the median filtering algorithm and realizing it, Describe the detailed method of realizing in FPGA through improve the median filtering algorithm. Introduce the project realization the system structure of the adoption.

关 键 词：现场可编程门阵列 中值滤波 实施图像处理 模块化设计 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]