40Gb/s 0.18μm CMOS甚短距离并行光接收前端放大器  

A 40Gb/s, 0.18μm CMOS front-end amplifier for VSR parallel optical receivers

作　　者：李智群[1] 薛兆丰[1] 王志功[1] 冯军[1] 章丽[1] 李伟[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《高技术通讯》2007年第6期591-594,共4页Chinese High Technology Letters

基　　金：863计划（2003AA312040）资助项目.

摘　　要：研制成功一种应用于甚短距离（VSR）光传输系统的40Gb/s并行光接收前端放大器芯片。该电路采用12路并行信道结构和0.18μm CMOS工艺,单信道传输速率达到了3.318Gb/s。电路设计采用了RGC结构和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题。提出了一种同时采用P＋保护环（PGR）、N＋保护环（NGR）和深N阱（DNW）的并行放大器隔离结构,有效地抑制了并行放大器之间的串扰,减小了放大器之间的衬底耦合噪声。测试表明,所有信道在3.318Gb/s数据速率、2mVpp输入和2pF的寄生电容下均得到了清晰的眼图。芯片采用1.8V电源供电,单路前端放大器的功耗为85mW,12路总功耗约为1W。A 40Gb/s imegrated parallel optical receiver front-end amplifier for VSR optical fiber transmission systems was developed. It was designed and fabricated in 0.18-μm CMOS technology and consisted of 12 channels inparallel with 3.318Gb/s per channel. A regnlated-cascede （RGC） structure and noise optimization were used in the design of transimpedance amplifier （TIA）, which overcomed the inadequate bandwidth problem caused by the large parasitical capacitor of CMOS photediede. An isolation structure combined with P^＋ guard-ring （PGR）, N^＋ guard-ring （NGR） and deepn-well （DNW） for parallel amplifier was also presented, which could effectively reduce the crosstalk and suppress the substrate noise coupling. The experimental results indicated that, with a parasitical capacitance of 2pF, a single channel was able to work at 3.318Gb/s and a clear eye diagram was obtained with a 2mVpp input. With a 1.8V supply, each channel of the front-end amplifier consumed 85mW, and the total power consumption of 12 channels was about 1 W.

关 键 词：并行光接收 前端放大器 RGC结构 衬底噪声耦合 放大器隔离 

分 类 号：TN929.11[电子电信—通信与信息系统]