High-performance, low-cost joint equalizer and trellis decoder for 1000BASE-T gigabit Ethernet transceiver  

作　　者：ZHU Yue RONG Meng-tian 

机构地区：[1]Department of Electronic Engineering, School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China

出　　处：《The Journal of China Universities of Posts and Telecommunications》2007年第2期106-111,共6页中国邮电高校学报（英文版）

基　　金：the National Science Foundation for Creative Research Groups （60521002）;Shanghai Natural Science Foundation （037062022）.

摘　　要：This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.

关 键 词：1000BASE-T GBE M-ALGORITHM PDFD look-ahead technology 

分 类 号：TN915[电子电信—通信与信息系统]