补偿流水线A/D转换器级间增益误差的后台校正技术  

Background Calibration for Compensating Interstage Gain Errors in Pipelined A/D Converters

作　　者：覃浩洋[1,2] 吴霜毅[1,2] 宁宁[1,2] 

机构地区：[1]电子薄膜和集成器件重点实验室 [2]电子科技大学微电子与固体电子学院,四川成都610054

出　　处：《微电子学》2007年第3期334-337,共4页Microelectronics

基　　金：国家自然科学基金资助项目(60072004)

摘　　要：在分析流水线A/D转换器中残差放大器电容匹配性和运放的有限增益引起的误差对信号传输影响的基础上,基于冗余位校正流水线A/D转换器结构,通过在信号通路中加入由伪随机码控制的校正信号测量上述误差的方法,在后台校正输出数字信号中的级间增益误差。通过Mat-lab对A/D转换器进行了系统级仿真。结果表明,12位A/D转换器系统的SFDR提高了31.8dB,SNDR提高了11.5 dB,INL减小了3.43 LSB,DNL减小了0.21 LSB。A background calibration technique is presented to compensate the interstage gain error in pipelined A/ D converters. A calibration signal is injected into input signal to participate in signal-process, which is controlled by pseudo random code. By using calibration signals, the interstage gain error can be measured and corrected at background. Simulations are performed for a 12-bit pipelined A/D converter using Matlab. It has been shown that the SFDR and SNDR of the A/D converter increases by 31.8 dB and 11.5 dB, respectively, and INL and DNL decreases by 3. 43 LSB and 0. 21 LSB, respectively.

关 键 词：流水线A/D转换器 级间增益误差 后台校正 伪随机码 

分 类 号：TN45[电子电信—微电子学与固体电子学]