快速数字电平转换电路IP核设计  

Design of IP core for high speed digital voltage shift circuit

作　　者：邹雪城[1] 孔令荣[1] 曾子玉[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《华中科技大学学报（自然科学版）》2007年第7期58-61,共4页Journal of Huazhong University of Science and Technology(Natural Science Edition)

摘　　要：基于IP核的技术设计了一种快速数字电平转换电路.采用电压-电流-电压的方式实现不同电压域的电平转换,引入单稳态延时电路和快慢速通道提高电平转换速度和降低静态功耗,并给出了与标准CMOS工艺兼容的扩展漏极高压MOS管的优化设计.仿真结果表明:在将-5^+5 V电压域的数字电平转换成0^+12V的电压域时,其延时可低于10 ns.A high speed digital voltage shift circuit based on IP core technology is proposed. Current mode approach was used to shift voltage from a voltage domain to another. Meanwhile a fast channel with constable time delay circuit and a slow channel were introduced to enhance voltage shifting speed and reduce quiescent power consumption. The circuit is compatible with standard complementary metal oxide semicenductor （CMOS） process. The simulation results indicated that the delay time was less than 10 ns when a voltage domain -5 - ＋5 V was shifted to another voltage domain 0 - ＋12 V.

关 键 词：互补金属氧化物半导体(CMOS) 电压域 电平转换 IP核 

分 类 号：TN453[电子电信—微电子学与固体电子学]