FPGA芯片中边界扫描电路的设计实现  

Design and Realization of Boundary-scan Test Circuit for FPGA's Chip

作　　者：于薇[1] 来金梅[1] 孙承绶[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路国家重点实验室,上海201203

出　　处：《计算机工程》2007年第13期251-254,共4页Computer Engineering

基　　金：上海AM基金资助项目(0406);国家"863"基金资助项目"FPGA专项"(2005AA1Z12305-2)

摘　　要：应用在FPGA芯片中的边界扫描电路侧重于电路板级测试,兼顾芯片功能测试,同时提供JTAG下载方式。FPGA芯片的规模越来越大,引脚数目越来越多,边界扫描单元也随之相应增加。在此情况下,边界扫描电路设计时为了避免移入错误数据,对时钟偏差提出了很高的要求。同时,由于扫描链包含大量的边界扫描单元,在板级测试时,大大降低了有效测试速率。针对这两个问题,提出了对边界扫描单元的改进方式,改进后的边界扫描电路不仅可实现测试、编程功能,而且大大提高了电路抗竞争能力,保证电路正常工作。改进后的电路使边界扫描寄存器链的长度可以改变,使有效测试速率提高了20倍左右。The boundary scan circuit （BSC） applied in the FPGA chip focuses on the PCB-level test and can provide JTAG program mode as well as the function test of the chip. Owing to the increasing pads of FPGA chip and the larger number of the corresponding BS cells, the clock skew is going to be the major consideration in circuit design to avoid the error of dala-input. Meanwhile, as BS chain contains a large number orBS cells, the effective test speed will be largely reduced during PCB-level test. In order to solve these problems, modification is made for the original structure of BSC. And the new generation of the BSC not only can realize the function of test, programming, but can provide significant immunity to races, thus, effectively guarantee the correct operation of the circuit. With the modified BSC, the boundary scan chain would be reconfigured to any desired length. In this way, it can improve the effective speed of PCB-level test.

关 键 词：边界扫描 现场可编程门阵列 时钟偏差 板级测试 

分 类 号：TP368.2[自动化与计算机技术—计算机系统结构]