基于Q矩阵准规则LDPC码半并行编码器的硬件实现  

Hardware Implementation of Partially-Parallel Encoder for Quasi-Regular LDPC Codes Based on Q-Matrix

作　　者：易燕[1] 申敏[1] 

机构地区：[1]重庆邮电大学移动通信工程研究中心,重庆400065

出　　处：《山西电子技术》2007年第4期5-6,11,共3页Shanxi Electronic Technology

基　　金：国家高技术研究发展计划(863计划)(2004AA123150)

摘　　要：LDPC码是一种逼近香农限的线性分组码,但其编码运算量较大,常具有码长的二次方复杂度。这里介绍Q矩阵特点和利用Q矩阵构造出的准规则LDPC码不仅可以具有中等码长和码率,而且还可以直接用H矩阵进行编码器设计,使编码运算量具有线性复杂度。然后使用Q矢量,简化了H矩阵存储量,采用半并行结构,提高了编码速度。最后使用Verilog硬件描述语言,在Xilinx Virtex2 XC2V1000上完成了物理实现,为LDPC码在通信系统的硬件实现与应用提供了很好参考设计。LDPC codes is a kind of linear group codes which can be near the Shannon limit, but the amount of operations about directly encoding LDPC Codes is large, the complexity of encoding is the square of the length of cedeword. In this article, it introduces how to construct LDPC codes with linearly encoding complexity used by Q-Matrix. Then it uses semi-pamllel architecture to simplify the complexity of multipliers, reduces the required memory for storing, and designs the effective coding algorithm based on Xilinx Virtex2 XC2V1000 in Verilog language by Xilinx ISE software. It can be supplied to the realization of hardware and actual application.

关 键 词：LDPC码 Q矩阵 半并行结构 

分 类 号：TN911.22[电子电信—通信与信息系统]