MAC在FPGA中的高效实现  

The High Efficient Realization of MAC with FPGA

作　　者：曹琦[1] 毕笃彦[1] 张齐[1] 

机构地区：[1]空军工程学院信号实验室,陕西西安710038

出　　处：《微计算机信息》2007年第17期216-218,共3页Control & Automation

摘　　要：乘累加器在DSP算法中有着举足轻重的地位。现在,很多前端DSP算法都通过FPGA实现。结合FPGA具体的硬件结构,提出了乘累加器在FPGA中实现的改进方法:流水线技术、CSD编码、DA算法,最后给出了这几种方法的实验结果。结果表明,这些方法的应用能大幅度的提高乘累加器在FPGA中的运行性能。　MAC plays a very important role in DSP algorithms. Nowadays, many front- side DSP algorithms are achieved through FPGA. Based on the specific hardware structure of the FPGA, this paper puts forward several methods to improve the achievement of MAC in FPGA. These methods include： pipeline technology, CSD encoding and DA algorithm. Then this paper provides the experimental results of these methods. It is concluded that they can greatly improve the performance of MAC in FPGA.

关 键 词：乘累加器 流水线 CSD编码 DA算法 

分 类 号：TN929.533[电子电信—通信与信息系统]