面向低功耗的全加器优化设计  

Optimization Design of Low Power Full Adder

作　　者：张爱华[1] 夏银水[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《微电子学》2007年第4期588-591,共4页Microelectronics

基　　金：国家自然科学基金资助项目(60676017);浙江省自然科学基金人才专项资助项目(R105614);宁波市自然科学基金资助项目(2006A610091)

摘　　要：在对现有全加器电路研究分析的基础上,提出了基于传输管逻辑的低功耗全加器。电路采用对称结构,平衡了电路延迟,消除了毛刺,降低了功耗。经PSPICE在0.24μm工艺下模拟仿真,与已发表的全加器电路的性能进行比较。测试结果表明,改进的新全加器功耗可减小77.5%,同时能耗也是最低的。Based on study and analysis of previous full adders, a novel low-power full adder using pass transistor logic was proposed, in which circuit delay was balanced, and so glitches were eliminated and power consumption was reduced in symmetry structure. SPICE simulation based on 0. 24μm process shows that the new full adder has power savings up to 77.5% and it also has the least power delay product, compared to published designs.

关 键 词：低功耗 全加器 传输晶体管 

分 类 号：TN432[电子电信—微电子学与固体电子学]