有限状态机在中断控制器设计中的应用  

Applecation of Finite-state Machine to Interrupt Controller Design

作　　者：王中[1] 爨莹[1] 

机构地区：[1]西安石油大学,西安710065

出　　处：《电脑开发与应用》2007年第9期10-11,23,共3页Computer Development & Applications

基　　金：陕西省自然科学基金基础研究计划项目(2005E205)

摘　　要：80386EX的中断控制器82C59A不论设置为边缘触发方式还是电平触发方式,均要求维持中断输入信号的高电平至第一个INTA#的下降沿结束,否则将产生误中断输出。由于系统内部及外部中断源中断方式不同,不能完全满足对电平持续时间的要求。为避免产生误中断,应用Mealy型有限状态机基本原理,提出通过在CPU和中断控制器两者之间加入Mealy型有限状态机,将中断输入信号和时序信号结合起来,输出满足中断控制器对高电平时序要求的中断信号,从而从根本上解决因时序引起的误中断输出问题。使用CPLD实现了这个设计,通过模拟仿真及实际应用,进一步论证了方案的合理性和可行性。实践证明这种设计方案可以很好的解决因时序产生的中断误输出问题,提高了中断响应的效率,在高速运算及精密控制方面有明显的优势。For both edge and level-triggered interrupts, a high level must be maintained on the IR line until after the falling edge of the first INTA #： pulse. A spurious interrupt request is generated if this stipulation is not met. On account of the different interrupt way between inside and outside of the system, it is incapable of adequately fulfill the need. In order to avoid the spurious interrupt, this thesis apply with the rationale of Mealy model finite-state machine that adding a finite-state machine between CPU and the interrupt controller, the high level could achieve the acknowledge cycle requirement of the interrupt controller, and solve radically the problem of spurious interrupt output on the basis of acknowledge cycle. The paper particularly demonstrates the rationality and the feasibility of the project by simulation. The practice testifies this kind of design can be good to resolve the spurious interrupt problem,enhanced the interrupt response efficiency, has the obvious advantage in the high-speed operation and the precise control.

关 键 词：有限状态机 中断控制器 中断时序 复杂可编程逻辑器件 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]