适于高速高精度多级ADC的功耗-速率优值模型  

A Power-Conversion Rate Merit Model for High-Speed High-Resolution ADC

作　　者：吴霜毅[1] 于奇[1] 王浩娟[1] 覃浩洋[1] 宁宁[1] 杨谟华[1] 

机构地区：[1]电子科技大学微电子与固体电子学院,成都610054

出　　处：《电子与信息学报》2007年第8期2006-2008,共3页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(60072004)资助课题

摘　　要：该文依据多级比较原理,建立了ADC功耗-速率优值模型。基于比较器数目最优算法,推导出多级ADC最优比较器数目,并提出多级ADC功耗-速率优值参数,从而得到可实现小功耗、高转换速率的多级ADC优化结构。以10位精度ADC为例,系统级仿真结果表明:多级ADC中的三级Pipelined结构可将全FlashADC功耗降低到最小,而保持相同的转换速率;同时理论验证了以两步式结构实现多级ADC优于其他多步式结构。该优值模型可应用于高速、高精度ADC系统结构优化。Based on multi-stage comparison, a new theory incorporating Minimum Comparator Number Algorithm （MCNA） and Power-Conversion Rate Merit Model （PCRMM） is proposed, which releases the power dissipation from limitation of comparators, sub-DACs and residual amplifiers in high-speed high-resolution ADCs. Under 10-bit ADC resolution specific, theoretical analysis shows that this theory reduces the power dissipation of Flash ADC to minimum by applying 3-stage Pipelined ADC, while keeping ADC high-speed, and it also proves that two-step ADC is better than other type of multi-step ADC. This new theory can be used in designing and developing high-speed low-power ADCs.

关 键 词：功耗-速率优值模型 模数转换器 比较器 低功耗 

分 类 号：TN432.1[电子电信—微电子学与固体电子学]