基于FPGA的串行接口时钟电路的设计  

Design of the Serial Interface Clock Circuit Based on FPGA

作　　者：郭来功[1] 

机构地区：[1]安徽理工大学,安徽淮南232001

出　　处：《现代电子技术》2007年第18期42-44,共3页Modern Electronics Technique

摘　　要：串行接口时钟芯片在电子系统中有着广泛的应用;介绍一种基于FPGA的多功能实时时钟芯片的设计方法,该芯片通过串行接口与外围通信;内置时钟提供了年、月、日、周、时、分、秒等信息,采用格雷码分频能减少系统功耗,内置RAM可以存储临时信息;仿真结果达到提出的要求,可以采用CSMC的0.6μm工艺进行流片。The serial interface clock chips are very popular in the using of electronic system. The article introduces a design method of multifunction real clock chip based on FPGA. The chip can communicate with peripheral unit by serial interface, embed real - time clock provides information on second, minute, hour, day, month, week and year. Using Gray code frequency can reduce the power consumption,embedded RAM may be used to store temporary information. Simulated result reaches the request suggesting,adopts 0.6 μm handicraft of CSMC to carry out produce.

关 键 词：FPGA 串行接口 VHDL 格雷码 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]