EPP增强型并行端口IP核的VLSI设计  

VLSI Design of EPP Enhanced Parallel Port IP Core

作　　者：姚霁[1] 

机构地区：[1]西安邮电学院,陕西西安710121

出　　处：《现代电子技术》2007年第18期47-49,共3页Modern Electronics Technique

摘　　要：提出一种EPP增强型并行端口IP核的VISL设计思想及实现方案。介绍了EPP并口以及IP核的知识,给出该IP核的硬件实现结构。提出的设计方法具有可扩展性好,实现灵活的特点。该IP核很容易通过编程的方式实现与多种外部设备通信,并不依赖于主机的模式限制,可广泛用于多种FPGA开发系统中。A design idea and an achieve project about IP core of EPP is put forward in this paper. The paper introduces the knowledge about EPP parallel port and IP core,and offers the configuration of the IP core. This method is expandable and flexible. It is easy to communicate with different peripheral equipments by programming and doesn＇t depend on the limitation of the host. It can be applied into the FPGA system widely.

关 键 词：EPP并口 IP核 VLSI FPGA 

分 类 号：TN409[电子电信—微电子学与固体电子学]