基于FPGA的大时宽带宽积频域脉压设计  

Design of a Large Time-bandwidth Product Pulse Compression in Frequency Domain with FPGA

作　　者：汪灏[1] 洪一[1] 

机构地区：[1]中国电子科技集团第38研究所,安徽合肥230031

出　　处：《现代电子技术》2007年第18期73-75,共3页Modern Electronics Technique

摘　　要：主要介绍基于Altera公司FPGA器件的高速实时FFT运算单元实现及频率域脉冲压缩处理的设计方法。在分析基8、按频率抽取FFT算法的基础上,采用多级同步流水线结构,利用现场可编程门阵列(FPGA)完成最大4 096点块浮点FFT。整个设计划分成多个功能模块,采用VHDL描述语言,并在Stratix器件上实现。结果表明,利用FPGA实现复杂的数字信号处理(DSP)算法是完全可行的。This paper is dedicated to the description of design and implementation of a high speed and real- time FFT and pulse compression in frequency domain processor with FPGA of Altera. Synchronously pipelined architecture which is based on FFT algorithm of Radix 8 and DIF （decimation in frequency） is utilized to achieve high throughput. To balance the precision and speed, the block floating point operation is adopted in each stage. The result indicate that the high- performance FPGA is suitable for complicated digital signal processing.

关 键 词：FFT 脉冲压缩 FPGA 块浮点 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]