面向存储系统的低功耗SoC设计  

Low Power Design for SoC Storage System

作　　者：黄少珉[1] 周凡[1] 张宇[1] 胡晨[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,南京210096

出　　处：《固体电子学研究与进展》2007年第3期402-407,共6页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(No60676011);教育部跨世纪优秀人才培养计划

摘　　要：降低存储系统功耗是SoC设计中的重要问题,基于对程序执行与器件特性的分析,在SDRAM中引入数据缓冲区,给出针对多进程数据访问特性的实现方法,降低了程序运行时外存设备的功耗。在EMI中实现了指令FIFO,并给出定制方法,降低了程序运行时的SDRAM能耗。实验与仿真表明,该方法能有效降低程序运行时SoC存储系统整体功耗。Reducing the power of storage system is an important goal in SoC design. Based on the analyses of program and device, this paper proposes a method for this goal. This method introduces data buffer in SDRAM in order to reduce the power of external memory in the environment of multi-process and instruction FIFO in EMI is implemented in order to reduce the energy consumed by SDRAM when program is running. Results of experiment and simulation showed that this method can reduce the overall power of SoC storage system when program is running.

关 键 词：低功耗 存储系统 片上系统设计 缓冲区 指令先入先出队列 

分 类 号：TN47[电子电信—微电子学与固体电子学]