一种低电压、高速CMOS运放的设计与仿真  

Design and simulation of a low-voltage and high-speed CMOS operational amplifier

作　　者：徐学恒[1] 于映[1] 

机构地区：[1]福州大学物理与信息工程学院,福州350002

出　　处：《国外电子测量技术》2007年第8期43-46,共4页Foreign Electronic Measurement Technology

摘　　要：本文设计了一种基于流水线ADC系统应用的低电压、高速运算放大器,该运放使用折叠式共源共栅结构、稳定的电压偏置电路、新型的共模反馈电路,使运放达到更高的性能。设计基于BSIM3V3 Spice模型,采用SMIC标准O.18μm CMOS工艺,用Cadence的Spectre工具对整个电路进行仿真。在1.8V单电源电压、2pF电容负载的工作条件下,仿真结果显示:直流开环增益为82dB,其单位增益带宽为260MHz,相位裕度60°,压摆率100V/μs,建立时间约10nS,功耗只有3.6mW,达到了设计要求。The design of a low-voltage, high-speed operational amplifier is based on the pipelined ADC. The operational amplifier gets better performance because of the fold-easeode structure, stable voltage-bias circuit, and new style CMFB circuit. The operational amplifier is based on BSIM3V3 Spice model, implemented in a standard 0. 18μm CMOS process, and simulated with Cadence Spectre. Results from simulation show that when the circuit worked in the single 1.8 V supply and 2 pF load capacitance has an open loop DC gain of 82 dB, a unity gain bandwidth of 260 MHz, SR of 100 V/μs, the settling time of 10 ns, and the total power consumption is only 3.6 mW.

关 键 词：CMOS 运算放大器 折叠式共源共栅 共模反馈 

分 类 号：TN433[电子电信—微电子学与固体电子学]