基于FPGA设计数字锁相环  

Design of DPLL Based on FPGA

作　　者：张秀平[1] 钟奇[2] 

机构地区：[1]河海大学计算机及信息工程学院,江苏常州213022 [2]江苏广播电视大学武进学院,江苏常州213161

出　　处：《河海大学常州分校学报》2007年第3期51-54,共4页Journal of Hohai University Changzhou

摘　　要：为了能在数字通信系统的接收端对信息进行正确译码,需产生一个用作取样判决的位定时脉冲.对采用数字锁相环提取定时脉冲的方法进行分析,提出了一种由微分超前/滞后型鉴相器构成数字锁相环的Verilog-HDL建模方案和基于FPGA实现该方案的设计过程,给出了仿真结果.以锁相环在CMI线路码译码中的应用为例,验证了该锁相环工作的可靠性.In order to decode accurately in receiver of digital communication system, timing pulse for bit is needed. Extracting method for timing pulse by DPLL is discussed. A realization scheme for DPLL composed of differential pull ahead＆lag phase detector is proposed. The Verilog-HDL program based on FPGA is introduced in detail and the simulation waveform is given. Finally, an example of applying in CMI decoder is demonstrated, The DPLL is tested and it works credibly.

关 键 词：数字锁相环 VERILOG-HDL 位定时脉冲 CMI译码 FPGA 

分 类 号：TN763.3[电子电信—电路与系统]