基于FPGA的大时宽带宽积频域脉压设计  

Design of a large time-bandwidth product pulse compression in frequency domain with FPGA

作　　者：汪灏[1] 洪一[1] 

机构地区：[1]中国电子科技集团公司第38研究所,安徽合肥230031

出　　处：《航天电子对抗》2007年第4期41-43,共3页Aerospace Electronic Warfare

摘　　要：介绍了基于ALTERA公司FPGA器件的高速实时FFT运算单元实现及频率域脉冲压缩处理的设计方法。在分析了基8、按频率抽取FFT算法的基础上,采用多级同步流水线结构,利用现场可编程门阵列(FPGA)完成了最大4096点块浮点FFT。整个设计划分成多个功能模块,采用VHDL描述语言,并在Stratix器件上实现。结果表明,利用FPGA实现复杂的数字信号处理(DSP)算法是完全可行的。The designs of a high speed and real-time FFT and pulse compression in frequency domain processor with the FPGA of ALTERA are introduced. Synchronously pipelined architecture based on the FFT algorithm of Radix 8 and DIF（decimation in frequency） is utilized to achieve high throughput. To balance precision and speed,the block floating point operation is adopted in each stage. The result indicates that the highperformance FPGA is suitable for complicated digital signal processing.

关 键 词：FFT 脉冲压缩 FPGA 块浮点 

分 类 号：TN957.51[电子电信—信号与信息处理]